1. Field of the Invention
The present invention relates to multiplexing transmission that transmits data via a transmission path.
2. Background Art
In recent years, many high speed serial data signals have been used in fields of mutually connecting LSIs and PCBs (printed circuit boards) that configure an information processing apparatus. In general, electric data signals are used for short distance transmission having a signal transmission distance equal to or less than several centimeters; optical data signals are used for long distance transmission having a signal transmission distance at least one meter. As signal transmission rates increase, the distance allowing transmission by electric data signals tends to be shorter and shorter. For instance, as a PCB that uniformizes wirings connecting PCBs to each other in an information processing apparatus (what is called a backplane PCB) has had an improved transmission rate of 10 Gbps or more, signals to be used for transmission has started to shift from electric data signals, which are difficult to transmit over a long distance, to optical data signals, which allow stable transmission.
The rate of transmission by optical data signals can be increased in comparison with the rate of transmission of electric data signals. Accordingly, the need intensifies for multiplexing many electric data signals on a PCB into a small number of optical data signals and transmitting the multiplexed signals. Thus, various techniques for multiplexing signals have been developed.
FIG. 1 shows a conventional multiplexer and de-multiplexer. A multiplexer circuit (the left in the drawing) used in this conventional circuit is required to operate in following conditions.
(1) Immediately before input into a multiplexer disposed at a final stage, all the data rates (X1 bps, . . . , Xn bps) of n inputs (TxP1, . . . , TxPn) are equal to each other. That is, X1=X2= . . . =Xn.
(2) The phases of all the pieces of bit data are the same as each other.
(3) The data rate of an output of the multiplexer is equal to the sum of the data rates of all the inputs. That is, Y=X1×n.
In general, a multiplexer circuit performs a process of converting a low speed parallel data signal (synchronization signals having the same speed and the same phase on all channels) into a high speed serial data signal. However, the conventional circuit shown in FIG. 1 does not have a mechanism ensuring that the number of an output channel of a de-multiplexer configuring a de-multiplexer circuit (the right in the drawing) coincides with the number of an input channel of a multiplexer circuit.
This type of mechanism is disclosed in JP Patent Publication (Kokai) No. 2000-252942 A. A multiplexer and de-multiplexer described in JP Patent Publication (Kokai) No. 2000-252942 A relates to a multiplexing process (specifically, SONET/SDH protocol) technique on optical data signals. A multiplexer circuit multiplexes low speed optical data signals to generate a high speed optical data signal, and a de-multiplexer circuit separates the high speed optical data signal to recover the initial low speed optical data signals.
FIG. 2 shows a configuration of a multiplexer and de-multiplexer circuit having a synchronization circuit disclosed in JP Patent Publication (Kokai) No. 2000-252942 A. A multiplexer circuit (the left in the drawing) shown in FIG. 2 terminates a specified protocol of only one channel among n+1 channels, and inserts a special pattern into the channel. The input, into which the special pattern has been inserted, is multiplexed by a (n+1):1 multiplexer into the other n inputs (TxP1, . . . , TxPn). That is, reframing is performed. In the drawing, a circuit used for generating the special pattern is denoted as a pattern generator.
Meanwhile, a de-multiplexer circuit (the right in the drawing) shown in FIG. 2 performs a special pattern synchronization process on a specified channel among separated n+1 channels. In the drawing, a circuit used for the special pattern synchronization is denoted as a pattern synchronizer. Through the synchronization process, the de-multiplexer circuit detects the leading position from which a 1:(n+1) de-multiplexer separates the multiplexed signal. Adoption of this mechanism allows the multiplexer and de-multiplexer shown in FIG. 2 to ensure the matching relationship between the numbers of the input channel and the output channel (hereinafter, the position of channel).
In the case of the circuit shown in FIG. 1, it is required to temporarily terminate the protocols of all the channels and concatenate data to multiplex the data. The circuit shown in FIG. 2 can keep the termination of the protocol to be only one channel. Accordingly, the apparatus of the circuit shown in FIG. 2 can be reduced in scale in comparison with the circuit shown in FIG. 1.
There is another method that temporally multiplexes packet data or frame data corresponding to inputs having different data rates and transmits the multiplexed data. A typical conventional art is a frame multiplexing apparatus standardized by the IEEE802 Committee (IEEE Std 802.3-2008). This frame multiplexing temporarily stores the frames of the channels having different data rates in a buffer, and subsequently reads the frames at the rate of an output channel, thereby realizing a multiplexing process on the channels having different data rates.
As described above, data transmission executed in an apparatus is required to handle many transmission channels. Accordingly, the apparatus and LSIs related to the data transmission are specifically required to be downsized.
However, in this type of use, the data rates of input channels to be multiplexed vary according to use situations. Accordingly, it is difficult to synchronize the data rates of all the channels input into the multiplexer. Furthermore, the data rates of the channels output from the de-multiplexer are required to completely coincide with the data rate of the respective corresponding input channels on the multiplexer side, in order to realize complete data transmission independent of the content of data to be transmitted on each channel without data loss. Thus, a realization method satisfying these conditions is required.
However, the multiplexer and de-multiplexer (FIG. 2) disclosed in JP Patent Publication (Kokai) No. 2000-252942 A cannot satisfy the conditions. This is because the circuit shown in FIG. 2 assumes that the rates of input channels are the same and realizes a multiplexing process on optical data signals by a simple multiplexer. That is, this is because the circuit configuration shown in FIG. 2 is incapable of multiplexing inputs having different data rates. Even if a process of terminating the SONET/SDH protocol is executed on a single channel, the required circuit scale is large. This is unsuitable for downsizing LSIs.
In contrast, a frame multiplexing apparatus disclosed in IEEE Std 802.3-2008 is capable of a multiplexing process of channels having different data rates.
However, the apparatus of IEEE Std 802.3-2008 is also incapable of causing the data rates of the input channel and the data rate of the output channel to completely coincide with each other. This is because accommodation of the difference between the data rates by framing loses clock information (clock frequency, frequency jitter, etc.) included in data on each channel at the time of input into the multiplexer. Furthermore, the apparatus of IEEE Std 802.3-2008 assigns destinations in units of frames and executes a process of dividing data according to the destinations, in order to ensure data transmission between the input channels and the output channels. This necessitates a process of searching for a destination for dividing data and a process of storing data for preventing data congestion. This fact means that the processing time required for data transmission cannot be strictly ensured. The aforementioned process requires a much larger circuit than that of the apparatus of JP Patent Publication (Kokai) No. 2000-252942 A. Accordingly, this process is very unsuitable for downsizing LSIs.
Furthermore, the invention disclosed in JP Patent Publication (Kokai) No. 2000-252942 A and the invention disclosed in IEEE Std 802.3-2008 cannot be combined together. This is because the apparatus of JP Patent Publication (Kokai) No. 2000-252942 A assumes that the input rates of channels be the same and multiplexes data on the channels. In contrast, the apparatus of IEEE Std 802.3-2008 is required to temporarily terminate the protocols of all channels and subsequently capture frames and execute a multiplexing process. Accordingly, an apparatus combining both the inventions leads to a result of losing an advantageous effect (reduction in apparatus scale) due to only one channel being terminated in JP Patent Publication (Kokai) No. 2000-252942 A. Even if both inventions are combined together, the data rate of the input channel and the data rate of the output channel cannot coincide with each other. Accordingly, the problem of IEEE Std 802.3-2008 cannot be solved.